1007ICT Digital Logic Circuit in The Logisim Simulator Assignment Sample

Computer Systems And Networks

Table of Contents

Details.

Circuit Details.

Part-A..

Part-B..

Circuit Diagram..

Part-A..

Part-B..

Circuit Analysis.

Truth Table.

References

Circuit Details

The circuit aims at the design of the digital circuit which will be applicable for car velocity and acceleration maintenance. In this circuit, there are different component and two significant part of operations. The complete circuit is constructed through Logisim (Ichsan & Kurniawan, 2017). Those are discussed below.

Circuit Details: Part-A

In this part of the circuit, two inputs are available namely Velocity and Acceleration. Both two has eight states and those are 0-7 meaning V_0-7 and A_0-7. The circuit will be operable concerning the combination of inputs.

The circuit has the following integrated parts:

1. Input: At the input side, the 3-to-8 Decoders is taken to generate 8 inputs from the 3 inputs of Velocity and Acceleration. The Decoder is designed in this project using basic gates that re NOT and AND gates. After preparing the input for Velocity and Acceleration with eight different states, the logic design is made to satisfy the conditions for the successful accelerations as provided in the requirement (Borodzhieva & Manoilov, 2018).
2. Comparator: The input of the system are combined using the Comapartor circuits which are built through the NAD gate and OR gate. This combinational circuit will show successful or unsuccessful acceleration. As the multi-input Gates are not allowed, so the stacking of the comparators have been designed at the input side to compare the Velocity and Acceleration both.
3. Output: A LED is connected at the output which will be lit when a successful acceleration will occur.

Circuit Details: Part-B

This section is specialized for keeping the count of the successful and unsuccessful acceleration made by the circuit input. This part is the extension of the Part-A circuit. As the output of the Part-A contains the LED which is acting as the indicator for the successful acceleration, this part will enrich the strategy by storing the records of the successful and unsuccessful acceleration (Tendeloo & Vangheluwe, 2013). For this objective, the Counter (3-bit) is used. As the Counter (3-bit) has the Delay input and the similar output is observed at the output (Q), so the outcome of the Pary-A circuit is extended to the Counter (3-bit) for keeping the records of the successful acceleration. On the other hand, another Counter (3-bit) is used to keep the record for the unsuccessful accelerations.

The Comparator is by taking the outputs of two Counter (3-bit) and compare for the outcome that is count. When the count of the unsuccessful record will be greater than the successful count, it sent “1” to the counter “0” port and disable it. This the circuit will be deactivated or locked (Borodzhieva & Manoilov, 2018).

Circuit Diagram

In this section, the circuit diagram is shown for two parts.

Circuit Diagram: Part-A

The circuit for part-A is as follows:

Circuit Diagram: Part-B

The circuit for part-B is as follows:

The analysis of the circuit can be done using the predefined option in the Logisim. Using the “Analyze Circuit”, the circuit analysis can be done and a segment of analysis of the truth table of the entire circuit is shown below (Ichsan & Kurniawan, 2017):

a b c DEN D0 d e f Output

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 1 0

0 0 0 0 0 1 0 0 0

After that the circuit statistics is obtained as follows:

Truth Table

As the circuit contains Velocity and Acceleration as the input and it also contains the output ports, the truth table of the circuit is as follows:

References for Computer Systems And Networks

Borodzhieva, A. N. & Manoilov, P. K., 2018. Decoder Synthesis in Teamwork Using Logisim. IEEE XXVII International Scientific Conference Electronics - ET.

Ichsan, M. H. H. & Kurniawan, W., 2017. Design and implementation 8 bit CPU architecture on Logisim for undergraduate learning support. International Conference on Sustainable Information Engineering and Technology (SIET).

Tendeloo, Y. V. & Vangheluwe, H., 2013. Logisim to DEVS Translation. IEEE/ACM 17th International Symposium on Distributed Simulation and Real Time Applications.

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