RAM-Based ALU Implementation Assignment Sample

Contents

Concept of RAM-Based ALU implementation

Operation of a four-bit Adder-Subtractor

Characteristics and requirements of the RAM and other peripherals

Implementation of Datapath

References

Concept of RAM-Based ALU Implementation

Reconfigurable systems combine hardware speed with software flexibility to improve performance as well as system performance, providing solutions to solve complex problems. In the last 30 years, technology has radically changed the way analysis as well as the world controls around it. The by-product of Intel's microprocessor development is the 8051 microcontroller, which is used at almost every stage. Microcontrollers are less known to the public as well as technical community than to the more attractive microprocessors. However, the general public is fully aware that "something" is the cause of all smart VCRs, watches-equipped radio, washing machines, dryers, video games, as well as television. The "something" is just a microcontroller. The microcontroller consists of three main components: arithmetic as well as logical units (ALU), random access memory (RAM), as well as read-only memory (ROM).

ALU is responsible for arithmetic operations as well as logical operations such as addition, subtraction, multiplication, as well as AND, OR, as well as NOT. The RAM is used to store as well as retrieve data as needed, as well as the ROM is used to store definitions for the execution of the operation code. This paper describes the design, development, as well as implementation of the Arithmetic as well as Logic Unit (ALU), Random Access Memory (RAM), as well as Read-Only Memory (ROM) for the 8051 microcontroller on the Field Programmable Gate Array (FPGA). Use of VHDL iee, VHSIC is an abbreviation for the ultra-fast integrated circuit VHSIC hardware description language. The Zylinks Spartan-3 xc3s50pq208-5 has been selected as the target FPGA device [1]. The ALU, RAM, as well as ROM device utilization has been analyzed as well as tabulated to explore the design space.

Operation of A Four-Bit Adder-Subtractor

In an advanced circuit, a paired snake/subtractor can both include just as take away twofold numbers in a solitary circuit itself. The activity performed relies upon the paired worth that the control signal holds. This is one of the parts of an ALU (number-crunching just as consistent unit).

This circuit requires Exor Gate, Binary Addition, and Subtraction, just as Full Adder.

For numerical activities, consider two 4-piece parallel A just as B as contribution to the computerized circuit

Since the activity is performed with a 4-piece number, the circuit comprises of four all adders. There is a control line K that holds a twofold estimation of 0 or 1, which confirms that the activity being performed is an expansion or deduction [2].

As appeared in the figure, the primary all adders straightforwardly have control lines as info (input transporter C0), just as information A0 (the most reduced piece of an) is legitimately contribution to all adders. The third information is B0 just as K's exor (S in the graph, yet don't mistake for Sum-S). The two yields produced are Sum/Difference (S0) just as Carry (C1).

In the event that the K (control line) esteem is 1, the yield is B0 (exor) K = B0 ' (supplement B0). Thusly, the activity is A + (B0 '). Presently, the two numbers A just as B are given two supplement deductions with A + B '. This infers if K = 1, the activity performed for the four bits is a deduction.

Thus, on the off chance that K = 0, at that point B0 (exor) K = B0. The activity is a straightforward parallel expansion, A + B. This infers if K = 0, the activity performed on the four piece checks is added substance.

At that point, C0 is passed as one of its yields to the second all adders in the sequential. All out/Difference S0 is recorded as the most minimal piece of aggregate/contrast. A1, A2, just as A3 are immediate contributions to the second, third, just as fourth all adders. The third info is B1, B2, just as B3, individually, just as EXOR to the second, third, just as fourth all adders in K. The carriages C1 just as C2 are passed to the sequential to the progressive all adders as one of the sources of info. C3 is the aggregate/distinction bearer. S1, S2, just as S3 are recorded to shape the aftereffect of S0 [3].

Characteristics and Requirements of The Ram and Other Peripherals

1. The determination lines MO just as M1 select the capacities that the ALU performs. You can join these choice lines with input contentions to make a guidance set.

2. These directions can be utilized to make significant projects. They should be effectively accessible too as can be put away in a ROM unit.

3. Input contentions A just as B is frequently put away in the inside register. These structure registers for microcontrollers, alongside other specific reason registers.

4. ROM memory is moderate. Along these lines, middle rapid RAM is regularly utilized.

5. All significant planning just as guidance deciphering is frequently joined into independent control just as timing units.

6. If the microcontroller comprises of just ALU, RAM, just as ROM, there is no outside interface. Along these lines, there is an I/O IO port.

7. 'Add extra highlights, for example, intrudes on, correspondence conventions, EEPROM, clocks/counters, just as troubleshoot interfaces, to finish the controller [4].

Implementation of Datapath

The heap/store information way utilizes directions, for example, LW $ t1, balance ($ t2), just as so on where counterbalanced is the memory address balance applied to the base location of register $ t2. The LW guidelines are perused from memory just as written to enroll $ t1. The sw guidance peruses from the register $ t1 just as composes it to memory. So as to compute the memory address, the MIPS ISA determination necessitates that a 16-piece counterbalance be marked just as stretched out to a 32-piece marked worth. This is finished utilizing the sign expansion appeared in the figure beneath.

The heap/store information way is appeared in the accompanying outline. The accompanying activities are acted in the predefined request:

Register get to takes contribution from the register record just as actualizes bring, disentangle, just as execute cycle guidelines, information, or address gets steps [5].

1. Memory location computation translates the base location just as counterbalance just as joins them to produce the real memory address. This technique utilizes a sign expansion just as an ALU.

2. Read/compose from memory gets information or directions from information memory just as actualizes the initial segment of the bring/disentangle/execute cycle execution step.

3. Writing to a register document composes information or directions to information memory just as actualizes the second piece of the get/disentangle/execute cycle execution step.

References for RAM-Based ALU Implementation

1. Kenneth J Ayala, West Carolina University, "The 8051 Microcontroller, Architecture, Programming and Applications", West Publishing Company, St Paul. ISBN 0-314-77278-2.

2. Online tutorial by MikroElektronika on "Architecture and programming of 8051 MCU's" http://www. mikroe. com/ chapters/view/64/chapter-1-introduction-to-microcontrollers.

3. Shrivastava Purnima, Tiwari Mukesh, Singh Jaikaran and Rathore Sanjay, "VHDL Environment for Floating point Arithmetic Logic Unit - ALU Design and Simulation", Research Journal of Engineering Sciences Vol. 1(2), 1-6, August (2012), ISSN 2278 – 9472,pp: 1-6

4. Shikha Khurana and Kanika Kaur "Implementation Of ALU Using FPGA" ,International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Volume 1, Issue 2, July – August 2012 ISSN 2278-6856, pp:146-149avel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.

5. Vandana Parihar and Dr. R. C. Jain, "Performance based Configuration and Implementation of Hash Processor" International Journal of Advance Technology & Engineering Research (IJATER) , Vol. 1, Issue 1, November 2011, ISSN NO: 2250-3536. Pp: 54-58.

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